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features q 2 0 ns maximum (5 volt supply) address ac c ess time q asynchronous operation for compatibility with industry- standard 512 k x 8 srams q ttl compatible inputs and o utput level s , three-state bidirectional data bu s q typical radiation performance - total dose : 5 0krads - >100krads(si), for any orbit, using aeroflex utmc patented shielded package - sel immune > 80 mev-cm 2 /m g - let th (0.25) = >1 0 mev-cm 2 /mg - s aturated cross section (cm 2 ) per bit, 5 .0e-9 - < 1e-8 errors/bit-day, adams to 90% geosynchronous heavy ion q packaging options: - 36-lead ceramic flatpack (weight 3.42 grams) - 36-lead flatpack shielded (weight 10.77 grams) q standard microcircuit drawing 5962-00536 - qml t and q c ompliant part introduction the qcots tm ut9q512 quantified commercial off-the- shelf product is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable ( e ) , an active low output enable ( g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the devic e i s accomplished by taking chip enable o ne ( e ) input low and write enable ( w ) inputs low. data on the eight i/o pins (dq 0 through dq 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable o ne ( e ) and output enable ( g ) low while forcing write enable ( w ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (dq 0 through dq 7 ) are placed in a high impedance state when the device is deselected ( e ) h igh), the outputs are disabled ( g high), or during a write operation ( e l owand w low). standard products qcots tm ut 9q 512 512k x 8 sram data sheet february, 2003 memory array 1024 rows 512x8 columns pre-charge circuit clk. gen. r o w s e l e c t a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 i/o circuit column select data cont rol clk gen. a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 5 a 1 6 a 1 7 a 1 8 dq 0 - dq 7 w g e figure 1. ut 9q 512 sram block diagram
2 pin names device operation the ut 9q 512 has three control inputs called enable 1 ( e ) , write enable ( w ), and output enable ( g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). e d evice enable c ontrols device selection, active, and standby modes. asserting e e nables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w greater than v ih (min) and e l ess than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram re ad cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable a nd output enable a re active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable - co ntrolled access in figure 3b, is initiated by e g oing active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram read cycle 3, the output enable - co ntrolled access in figure 3c, is initiated by g going active while e i s asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address dq(7:0) data input/output e enable w write enable g output enable v dd power v ss ground 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 figure 2 . ut 9q 512 25ns sram pinout (36) (for both shielded and unshielded packages) nc a18 a17 a16 a15 g dq7 dq6 v ss v dd dq5 dq4 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 e dq0 dq1 v dd v ss dq2 dq3 w a5 a6 a7 a8 a9 g w e i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read
3 write cycle a combination of w less than v il (max) and e l ess than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable - co ntrolled access in figure 4a, is defined by a write terminated by w going high, with e s till active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e . unless the outputs have been previously placed in the high- impedance state by g , the user must wait t wlqz before applying data to the nine bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable - co ntrolled access in figure 4b, is defined by a write terminated by e g oing inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by the e g oing active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. typical r adiation hardness table 2. radiation hardness design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. 10% worst case particle environment, geosynchronous orbit, 0.025 mils of aluminum. total dose 50 k rad(si) heavy ion error rate 2 <1e-8 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 5 t o 7.0v v i/o voltage on any pin -0. 5 t o 7.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 4.5 t o 5.5v t c case temperature range (c) screening: -55 to +125 c (e) screening: -40 to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* (-55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening ) (v dd = 5.0v + 10%) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 . 1. measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second . symbol parameter condition min max unit v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v v ol1 low-level output voltage i ol = 8ma, v dd =4.5v 0.4 v v o l2 low-level output voltage i ol = 200 m a,v dd = 4.5v 0.05 v v oh 1 high-level output voltage i oh = -4ma,v dd =4.5v 2.4 v v oh 2 high-level output voltage i oh = -200 m a,v dd =4.5v 3.2 v c in 1 input capacitance | = 1mhz @ 0v 10 pf c io 1 bidirectional i/o capacitance | = 1mhz @ 0v 1 2 pf i in input leakage current v in = v dd and v ss , v dd = v dd (max) -2 2 m a i oz three-state output leakage current v o = v dd and v ss v dd = v dd (max) g = v dd (max) -2 2 m a i os 2, 3 short-circuit output current v dd = v dd (max), v o = v dd v dd = v dd (max), v o = 0v -90 90 ma i dd (op) supply current operating @ 1mh z inputs: v il = 0 . 8v , v ih = 2.0v i out = 0 ma v dd = v dd (max) 125 ma i dd1 (op) supply current operating @40mh z i nputs: v il = 0 . 8v , v ih = 2.0 v i out = 0 ma v dd = v dd (max) 180 ma i dd 2 ( sb) supply current standb y @0mh z i nputs: v il = v ss i out = 0 ma e = v dd - 0. 5 v dd = v dd (max) v ih = v dd - 0. 5 v 6 6 12 ma ma ma -55 c and 2 5 c -40 c and 25 c 1 25 c
6 ac characteristics read cycle ( pre/ post-radiation)* (-55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening ) (v dd = 5.0v + 10%) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 50 0mv change from steady-state output voltage (see figure 3). 3. the et (enable true) notation refers to the falling edge of e . seu immunity does not affect the read parameters. 4. the ef (enable false) notation refers to the rising edge of e . seu immunity does not affect the read parameters. symbol parameter min max unit t avav 1 read cycle time 2 0 ns t avqv read access time 25 ns t axqx output hold time 3 ns t glqx g -controlled output enable t ime 0 ns t glqv g -controlled output enable t ime (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 3 e - controlled output enable t ime 3 ns t etqv 3 e - controlled access time 25 ns t efqz 1, 2, 4 e - controlled output three-state time 10 ns { { } } v load + 500mv v load - 500mv v load v h - 500mv v l + 500mv active to high z levels high z to active levels figure 3. 5-volt sram loading
7 assumptions: 1. e a nd g < v il (max) and w > v i h ( min) a(18:0) dq(7:0) figure 4a . sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w > v ih (min) a(18:0) figure 4b . sram read cycle 2: chip enable -controlled access e data valid t efqz t etqv t etqx dq(7:0) figure 4c . sram read cycle 3: output enable -controlled access a(18:0) dq(7:0) g t ghqz assumptions: 1. e < v il (max) and w > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycle ( pre/ post-radiation)* (-55 c to +125 c for (c) screening and -40 o c to +125 o c for (e) screening ) (v dd = 5. 0v + 10%) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performed with outputs disabled ( g high). 2. three-state is defined as 50 0mv change from steady-state output voltage (see figure 3). symbol parameter 9q 512-25 5.0v min max unit t avav 1 write cycle time 2 0 ns t etwh device enable t o end of write 20 ns t avet address setup time for write ( e - controlled) 0 ns t avwl address setup time for write ( w - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write ( w - controlled) 0 ns t efax address hold time for device enable ( e - controlled) 0 ns t wlqz 2 w - controlled three-state time 10 ns t whqx w - controlled output enable t ime 5 ns t etef device enable p ulse width ( e - controlled) 20 ns t dvwh data setup time 15 ns t whdx data hold time 2 ns t wlef device enable c ontrolled write pulse width 20 ns t dvef data setup time 15 ns t efdx data hold time 2 ns t avwh address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then q( 7: 0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w t avwl figure 5a . sram write cycle 1: write enable - c ontrolled access a(18:0) q(7:0) e t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl
10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e s cenario above can occur. 3 . g high for t avav cycle. a(18:0) figure 5b . sram write cycle 2: chip enable - controlled access w e d(7:0) applied data e q(7:0) t wlqz t etef t wlef t dvef t avav 3 t avet t avet t etef t efax t efax or notes: 1. 50pf including scope probe and test sock et capacitance. 2. measurement of data output occurs at the low to high or high to low transition mid-point (i.e., cmos input = v dd /2). 90% figure 6. ac test loads and input waveforms input pulses 10% < 5ns < 5ns v load = 1.55v 300 o hms 50pf cmos 0.5v v dd -0.05v 10%
11 d ata retention characteristics (pre/post- irra diation) ( 1 s ec ond data retention test) notes: 1. e = v dd - .2v, all other inputs = v dr or v ss . 2. data retention current (i ddr ) tc = 25 o c. 3. not guaranteed or tested. data retention characteristics (pre/post-irradiation) ( 10 second data retention test, tc= -55 o c to 125 o cf or (c) screening and -40 o c to +125 o c for (e) screening ) notes: 1. performed at v dd (min) and v dd (max). 2. e = v ss , all other inputs = v dr or v ss . 3. not guaranteed or tested. symbol parameter minimum maximum unit v dr v dd for data retention 2. 5 -- v i ddr 1 ,2 data retention current -- 5. 0 ma t efr 1 , 3 chip select to data retention time 0 ns t r 1 , 3 operation recovery time t avav ns symbol parameter minimum maximum unit v dd 1 v dd for data retention 4. 5 5.5 v t efr 2, 3 chip select to data retention time 0 ns t r 2, 3 operation recovery time t avav ns v dd data retention mode t r 50% 50% v dr > 2.5v figure 7. low v dd data retention waveform t efr e
12 p ackaging figure 8. 36-pin ceramic flatpack 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance to mil-prf-38535. 4. lead position and coplanarity are not measured. 5. id mark is vendor option. 6. total weight is approx. 3.42g.
13 1. a ll package finishes are per m il-prf-38535. 2. letter designations are for cross-reference to mil-std-1835. 3. all leads increase max. limit by 0.003 measured at the center of the flat, when lead finish a (solder) is applied. 4. total weight is approx. 10. 77 g. 5. x-rays are an ineffective test for shielded packages. . figure 9. 36-lead flatpack shielded package
14 ordering information 512 k x 8 s ram: = 25ns access time, 5.0v operation 20 = 20ns access time, 5.0v operation package type: (i) = 36 -lead flatpack shielded package (bottom brazed) (u) = 36-lead flatpack package ( bottom brazed) screening: (c) = military temperature range flow (p) = prototype flow (w) = extended industrial temperature range flow ( -40 o c to +125 o c) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and +125 c. radiation neither tested nor guaranteed. 5. 36lbbfp shielded package f or reduced high rel orders only. 6. extended industrial temperature range flow per utmc manufacturing flows document. devices are tested at -40 c to +125 c. radiation neither tested nor guaranteed. ut9q512 - * * * * -aeroflex utmc core part number
15 512k x 8 sram: smd 5962 - 00536 lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 36-lead flatpack shielded package (bottom brazed) ( u ) = 36-lead ceramic flatpack (b ottom-brazed ) class designator: (t) = qml class t (q) = qml class q device type 01 = 25ns access time, 5.0v operation, mil-temp 02 = 25ns access time, 5.0v operation, extended industrial temp (-40oc to +125oc) 03 = 20ns access time, 5.0v operation, mil-temp 04 = 20ns access time, 5.0v operation, extended industrial temp (-40oc to +125oc) drawing number: 00536 total dose : ( d) = 1e4 (10 kr ad)(si)) (p) = 3e4 (30 krad)(si)) , contact factory (l) = 5e4 (50krad(si)), contact factory federal stock class designator: no options * * * ** notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering.

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